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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This is the main header file for Xilinx HDMI TX core. </p>
<p>HDMI TX core is used for transmitting the incoming video and audio streams. It consists of</p>
<ul>
<li>Transmitter core</li>
<li>AXI4-Stream to Video Bridge</li>
<li>Video Timing Controller and</li>
<li>High-bandwidth Digital Content Protection (HDCP) (Optional).</li>
</ul>
<p>The HDMI TX uses three AXI interfaces for Video, Audio and Processor:</p>
<ul>
<li>AXI4-Stream interface for Video, can be single, dual or quad pixels per clock and supports 8 and 10 bits per component.</li>
<li>AXI4-Stream interface for Audio, accepts multiple channels uncompressed and compressed audio data.</li>
<li>AXI4-Lite interface for processor, controls the transmitter. Please do refer AXI Reference Guide (UG761) for more information on AXI interfaces.</li>
</ul>
<p>Transmitter core performs following operations:</p>
<ul>
<li>Converts video data from the video clock domain into the link clock domain.</li>
<li>TMDS (Transition Minimized Differential Signaling) encoding.</li>
<li>Merges encoded video data and packet data into a single HDMI stream.</li>
<li>Optional HDMI stream is encrypted by an external HDCP module.</li>
<li>Over samples HDMI stream if stream bandwidth is too low for the transceiver to handle.</li>
<li>Scrambles encrypted/HDMI stream if data rate is above 3.4 Gbps otherwise bypasses the Scrambler.</li>
</ul>
<p>AXI Video Bridge converts the incoming video AXI-stream to native video.</p>
<p>Video Timing Controller (VTC) generates the native video timing.</p>
<p><b>Core Features </b></p>
<p>For a full description of HDMI TX features, please see the hardware specification.</p>
<p><b>Software Initialization &amp; Configuration</b></p>
<p>The application needs to do following steps in order for preparing the HDMI TX core to be ready.</p>
<ul>
<li>Call XV_HdmiTx1_LookupConfig using a device ID to find the core configuration.</li>
<li>Call XV_HdmiTx1_CfgInitialize to initialize the device and the driver instance associated with it.</li>
</ul>
<p><b>Interrupts </b></p>
<p>This driver provides interrupt handlers</p>
<ul>
<li>XV_HdmiTx1_IntrHandler, for handling the interrupts from the HDMI TX core PIO and DDC peripheral respectively.</li>
</ul>
<p>Application developer needs to register interrupt handler with the processor, within their examples. Whenever processor calls registered application's interrupt handler associated with interrupt id, application's interrupt handler needs to call appropriate peripheral interrupt handler reading peripheral's Status register.</p>
<p>This driver provides XV_HdmiTx1_SetCallback API to register functions with HDMI TX core instance.</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
<p><b> Building the driver </b></p>
<p>The HDMI TX driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
<pre>
 MODIFICATION HISTORY:
s
 Ver   Who    Date     Changes
</p>
<hr/>
<p>
 1.00  EB     22/05/18 Initial release.
 </pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1___frl.html">XV_HdmiTx1_Frl</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains audio stream specific data structure.  <a href="struct_x_v___hdmi_tx1___frl.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a278ba63cb581ced213ae23aabafe201b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a278ba63cb581ced213ae23aabafe201b">XV_HDMITX1_FRL_H_</a></td></tr>
<tr class="memdesc:a278ba63cb581ced213ae23aabafe201b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a278ba63cb581ced213ae23aabafe201b">More...</a><br/></td></tr>
<tr class="separator:a278ba63cb581ced213ae23aabafe201b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI TX FRL training state</div></td></tr>
<tr class="memitem:a835a33b58542988390ee91c443f6359d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_FrlTrainingState</b> </td></tr>
<tr class="separator:a835a33b58542988390ee91c443f6359d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI TX LTP Type</div></td></tr>
<tr class="memitem:afd0877f78089682c46d57eb1012ba6e9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_FrlLtpType</b> </td></tr>
<tr class="separator:afd0877f78089682c46d57eb1012ba6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
HDMI TX FRL Active Mode</h2></td></tr>
<tr class="memitem:aaa2b17ec29b80b19f9fa18abadeef78b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#aaa2b17ec29b80b19f9fa18abadeef78b">XV_HdmiTx1_FrlIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aaa2b17ec29b80b19f9fa18abadeef78b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI TX FRL peripheral.  <a href="#aaa2b17ec29b80b19f9fa18abadeef78b">More...</a><br/></td></tr>
<tr class="separator:aaa2b17ec29b80b19f9fa18abadeef78b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58012592af0eafb0b1bdbce08aa70169"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a58012592af0eafb0b1bdbce08aa70169">XV_HdmiTx1_FrlIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a58012592af0eafb0b1bdbce08aa70169"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI TX FRL peripheral.  <a href="#a58012592af0eafb0b1bdbce08aa70169">More...</a><br/></td></tr>
<tr class="separator:a58012592af0eafb0b1bdbce08aa70169"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a22ee7036ae97717d94a76b551a6ade52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a22ee7036ae97717d94a76b551a6ade52">XV_HdmiTx1_FrlRcEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a22ee7036ae97717d94a76b551a6ade52"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral.  <a href="#a22ee7036ae97717d94a76b551a6ade52">More...</a><br/></td></tr>
<tr class="separator:a22ee7036ae97717d94a76b551a6ade52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2502d7c8116ff5b4586bf81e0001296b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a2502d7c8116ff5b4586bf81e0001296b">XV_HdmiTx1_FrlRcDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2502d7c8116ff5b4586bf81e0001296b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral.  <a href="#a2502d7c8116ff5b4586bf81e0001296b">More...</a><br/></td></tr>
<tr class="separator:a2502d7c8116ff5b4586bf81e0001296b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2190d9b351c0d93b52da5ecdf7d0ccc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a2190d9b351c0d93b52da5ecdf7d0ccc8">XV_HdmiTx1_SetFrlLinkClock</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a2190d9b351c0d93b52da5ecdf7d0ccc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the link clock of TX Core's FRL peripheral.  <a href="#a2190d9b351c0d93b52da5ecdf7d0ccc8">More...</a><br/></td></tr>
<tr class="separator:a2190d9b351c0d93b52da5ecdf7d0ccc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d9362b70a136651d8c779620a25af58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#a0d9362b70a136651d8c779620a25af58">XV_HdmiTx1_SetFrlVidClock</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a0d9362b70a136651d8c779620a25af58"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the video clock of TX Core's FRL peripheral.  <a href="#a0d9362b70a136651d8c779620a25af58">More...</a><br/></td></tr>
<tr class="separator:a0d9362b70a136651d8c779620a25af58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada7516a3ce97e28980629b26677ec4b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#ada7516a3ce97e28980629b26677ec4b4">XV_HdmiTx1_FrlRateLockEnable</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Frl.RateLock = TRUE</td></tr>
<tr class="memdesc:ada7516a3ce97e28980629b26677ec4b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables FRL Rate Lock.  <a href="#ada7516a3ce97e28980629b26677ec4b4">More...</a><br/></td></tr>
<tr class="separator:ada7516a3ce97e28980629b26677ec4b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adeff1a67ca25514ca8095cefbdb2a937"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1__frl_8h.html#adeff1a67ca25514ca8095cefbdb2a937">XV_HdmiTx1_FrlRateLockDisable</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Frl.RateLock = FALSE</td></tr>
<tr class="memdesc:adeff1a67ca25514ca8095cefbdb2a937"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables FRL Rate Lock.  <a href="#adeff1a67ca25514ca8095cefbdb2a937">More...</a><br/></td></tr>
<tr class="separator:adeff1a67ca25514ca8095cefbdb2a937"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b99df30b0bf9c96608c0167750bbfb6"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_FrlActiveMode</b> </td></tr>
<tr class="separator:a5b99df30b0bf9c96608c0167750bbfb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a278ba63cb581ced213ae23aabafe201b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX1_FRL_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a58012592af0eafb0b1bdbce08aa70169"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_FrlIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a143c3655dacc300a41dac7cbe34c4ed7">XV_HDMITX1_FRL_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa5da06390a2ac2dc17a7581c3cc7f81a"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_CLR_OFFSET</div><div class="ttdoc">FRL Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:571</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a143c3655dacc300a41dac7cbe34c4ed7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a143c3655dacc300a41dac7cbe34c4ed7">XV_HDMITX1_FRL_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_IE_MASK</div><div class="ttdoc">FRL Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:600</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI TX FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#a58012592af0eafb0b1bdbce08aa70169" title="This macro disables interrupt in the HDMI TX FRL peripheral. ">XV_HdmiTx1_FrlIntrDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="aaa2b17ec29b80b19f9fa18abadeef78b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_FrlIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a143c3655dacc300a41dac7cbe34c4ed7">XV_HDMITX1_FRL_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a143c3655dacc300a41dac7cbe34c4ed7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a143c3655dacc300a41dac7cbe34c4ed7">XV_HDMITX1_FRL_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_IE_MASK</div><div class="ttdoc">FRL Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:600</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ae76270b448224670d8cd9615dbac2091"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_SET_OFFSET</div><div class="ttdoc">FRL Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:568</div></div>
</div><!-- fragment -->
<p>This macro enables interrupt in the HDMI TX FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#aaa2b17ec29b80b19f9fa18abadeef78b" title="This macro enables interrupt in the HDMI TX FRL peripheral. ">XV_HdmiTx1_FrlIntrEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_FrlRateLockDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Frl.RateLock = FALSE</td>
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<p>This macro disables FRL Rate Lock. </p>
<p>With FRL Rate Lock disabled, TX core will behave according to the HDMI spec and will drop FRL Rate when the sink requests to drop FRL rate.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#adeff1a67ca25514ca8095cefbdb2a937" title="This macro disables FRL Rate Lock. ">XV_HdmiTx1_FrlRateLockDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_FrlRateLockEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Frl.RateLock = TRUE</td>
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<p>This macro enables FRL Rate Lock. </p>
<p>With FRL Rate Lock enabled, TX core will not change to any other FRL Rate even when it is requested by the sink to drop FRL rate.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#ada7516a3ce97e28980629b26677ec4b4" title="This macro enables FRL Rate Lock. ">XV_HdmiTx1_FrlRateLockEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_FrlRcDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a796e498d647fa273f085bc9a561b32b0">XV_HDMITX1_FRL_CTRL_TST_RC_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a796e498d647fa273f085bc9a561b32b0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a796e498d647fa273f085bc9a561b32b0">XV_HDMITX1_FRL_CTRL_TST_RC_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_TST_RC_MASK</div><div class="ttdoc">FRL RC Compress mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:612</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ae76270b448224670d8cd9615dbac2091"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_SET_OFFSET</div><div class="ttdoc">FRL Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:568</div></div>
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<p>This macro disables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#a2502d7c8116ff5b4586bf81e0001296b" title="This macro disables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral...">XV_HdmiTx1_FrlRcDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_FrlRcEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a796e498d647fa273f085bc9a561b32b0">XV_HDMITX1_FRL_CTRL_TST_RC_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa5da06390a2ac2dc17a7581c3cc7f81a"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_CLR_OFFSET</div><div class="ttdoc">FRL Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:571</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a796e498d647fa273f085bc9a561b32b0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a796e498d647fa273f085bc9a561b32b0">XV_HDMITX1_FRL_CTRL_TST_RC_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_CTRL_TST_RC_MASK</div><div class="ttdoc">FRL RC Compress mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:612</div></div>
</div><!-- fragment -->
<p>This macro enables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#a22ee7036ae97717d94a76b551a6ade52" title="This macro enables repeat count in the packetizer (with RC compress) in the HDMI TX FRL peripheral...">XV_HdmiTx1_FrlRcEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_SetFrlLinkClock</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">	XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#abcfb2ad0c96c0240bd2211dba81810d0">XV_HDMITX1_FRL_LNK_CLK_OFFSET</a>), \</div>
<div class="line">                            (Value)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_abcfb2ad0c96c0240bd2211dba81810d0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#abcfb2ad0c96c0240bd2211dba81810d0">XV_HDMITX1_FRL_LNK_CLK_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_LNK_CLK_OFFSET</div><div class="ttdoc">FRL Link Clock Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:580</div></div>
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<p>This macro sets the link clock of TX Core's FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the Link Clock</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#a2190d9b351c0d93b52da5ecdf7d0ccc8" title="This macro sets the link clock of TX Core&#39;s FRL peripheral. ">XV_HdmiTx1_SetFrlLinkClock(XV_HdmiTx1 *InstancePtr, u16 Value)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_SetFrlVidClock</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">	XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ae77246dd4776e8a41f7b92c093c4e1a0">XV_HDMITX1_FRL_VID_CLK_OFFSET</a>), \</div>
<div class="line">                            (Value)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ae77246dd4776e8a41f7b92c093c4e1a0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ae77246dd4776e8a41f7b92c093c4e1a0">XV_HDMITX1_FRL_VID_CLK_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_FRL_VID_CLK_OFFSET</div><div class="ttdoc">FRL Video Clock Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:583</div></div>
</div><!-- fragment -->
<p>This macro sets the video clock of TX Core's FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the Video Clock</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1__frl_8h.html#a0d9362b70a136651d8c779620a25af58" title="This macro sets the video clock of TX Core&#39;s FRL peripheral. ">XV_HdmiTx1_SetFrlVidClock(XV_HdmiTx1 *InstancePtr, u16 Value)</a> </dd></dl>

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